1. Field of Invention
The present invention relates to a ring oscillator circuit, an analog-to-digital (AD) conversion circuit, and a solid-state imaging apparatus.
Priority is claimed on Japanese Patent Application No. 2011-150080, filed on Jul. 6, 2011, the content of which is incorporated herein by reference.
2. Description of Related Art
In the related art, methods using a ring oscillator circuit having a configuration of an odd number of inverting circuits (stages), which are connected in a ring and each invert an input signal to output the inverted input signal, when the time is converted into a digital value, are well-known. This ring oscillator circuit functions as an oscillation circuit that causes a pulse edge to circulate around the ring. Technology for converting the time into a digital value by detecting the number of inverting circuits (stages) through which a pulse edge has passed and converting the detected number of inverting circuits (stages) into a binary number is well-known.
For example, technology disclosed in Japanese Unexamined Patent Application, First Publication No. H03-220814 is a pulse phase difference encoding circuit using a ring oscillator circuit as described above, which is referred to as an analog-to-digital (A/D) conversion circuit. Also, an integral A/D conversion circuit, a single-slope A/D conversion circuit, and the like are well-known as an A/D conversion circuit using the ring oscillator circuit for converting the time into a digital value. The A/D conversion circuit using the above-described ring oscillator circuit is applied to a solid-state imaging apparatus having a built-in A/D conversion circuit because the entire A/D conversion circuit can be implemented by a digital circuit.
In addition, for example, in Japanese Unexamined Patent Application, First Publication No. H06-216721, technology for implementing a ring oscillator circuit in which an even number of inverting circuits (stages) are connected in a ring is disclosed. In the technology disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721, the number of times a pulse edge has circulated around the ring oscillator circuit constituted by an even number of inverting circuits (stages) and the number of inverting circuits (stages) that do not satisfy one round in which the pulse edge has passed through inverting circuits within the ring oscillator circuit are detected. Conversion of the number of inverting circuits of the ring oscillator circuit through which the pulse edge has passed into a binary number is performed by designating the detected number of circulations as more significant bits, designating the detected number of inverting circuits (stages) as less significant bits, converting each number into a binary number, and connecting the more significant bits and the less significant bits.
Thereby, it is possible to simplify a complex calculation process according to the conversion into a binary number in the technology disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721.
Here, a specific example of a ring oscillator circuit disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721 will be described. FIG. 12 is a block diagram illustrating an example of a schematic configuration of the ring oscillator circuit of the related art disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721. In FIG. 12, the case in which negative AND circuits (NAND circuits) and logical NOT circuits (inverter circuits) are combined and configured as inverting circuits is illustrated as an example of a ring oscillator circuit constituted by 16 (stage) inverting circuits. More specifically, as illustrated in FIG. 12, the ring oscillator circuit 180 includes NAND circuits I1 and I12 and inverter circuits I2 to I1 and I13 to I16.
The NAND circuit I1 functions as a first starting inverting circuit that starts driving of a first pulse signal (hereinafter referred to as “main pulse”) based on a control signal. The NAND circuit I12 functions as a second starting inverting circuit that starts driving of a second pulse signal (hereinafter referred to as “reset pulse”) based on the main pulse. The other inverter circuits I2 to I11 and I13 to I16 function as inverting circuits that transfer the input main pulse and reset pulse to the inverting circuits of the next stages.
The NAND circuit I1 starts driving of the main pulse by inverting the input control signal. The NAND circuit I12 starts driving of the reset pulse based on the input main pulse after the main pulse is transferred and output from the inverter circuit I4. In addition, the NAND circuit I1 resets the main pulse based on the input reset pulse after the reset pulse is transferred and output from the inverter circuit I16. Thereafter, the NAND circuit I1 restarts driving of the main pulse based on the input previous main pulse after the previously driven main pulse is transferred and output from the inverter circuit I16.
As described above, in the ring oscillator circuit 180, the NAND circuit I1 drives the main pulse, the NAND circuit I12 drives the reset pulse, and the inverter circuits I2 to I11 and I13 to I16 transfer the input main pulse and reset pulse, so that an oscillation operation is performed.
Next, an operation of the ring oscillator circuit disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721 will be more specifically described. In the following description, the NAND circuit I1, the inverter circuits I2 to I11, the NAND circuit I12, and the inverter circuits I13 to I16 illustrated in FIG. 12 are referred to as the inverting circuits I1 to I16, respectively. FIG. 13 is a diagram illustrating operations of the inverting circuits within the ring oscillator circuit 180 of the related art. FIG. 13 illustrates a state of a signal (hereinafter referred to as “node”) of an output terminal of each inverting circuit under the assumption that delay times required for signal inversions of the inverting circuits I1 to I16 are identical.
Numerals 1 to 16 illustrated in FIG. 13 correspond to nodes of the inverting circuit I1 to I16 illustrated in FIG. 12. In addition, “o: white circle” illustrated in FIG. 13 indicates that each node is in the reset state, and “●: black circle” indicates that each node is in a set state. The logic of the reset state and the set state of the inverting circuits I1 to I16 is denoted by “L” or “H” within FIG. 13. “L” represents that the inverting circuits I1 to I16 output a signal of a “Low” level. “H” represents that a signal of a “High” level is output. In addition, in “X”th-round inversion “Y” illustrated in FIG. 13, “X” represents that main-pulse circulation is “X”th-round, and “Y” denotes a time when one node has changed from a previous state. Thereby, in FIG. 13, node positions in which a pulse edge of the main pulse and a pulse edge of the reset pulse are positioned within the ring oscillator circuit 180 are schematically illustrated.
The transition of a basic operation of the ring oscillator circuit 180 will be described with reference to FIG. 13.
In FIG. 13, a state of 0th-round inversion 0 is a state in which the control signal has the “Low” level, the ring oscillator circuit 180 is reset, and no main pulse occurs. Thereafter, the control signal has the “High” level, so that the ring oscillator circuit 180 starts the operation. If the control signal has the “High” level, the inverting circuit I1 is switched from the reset state to the set state in 0th-round inversion 1, so that the main pulse is generated and the state of the node 1 is switched to the set state.
Thereafter, the main pulse is sequentially transferred to the inverting circuits I2 to I4 of the next stages, so that the states of the nodes 2 to 4 are sequentially switched to the set state. In 0th-round inversion 5, the inverting circuit I12 is switched from the set state to the reset state according to the state of the node 4, so that the reset pulse is generated and the state of the node 12 is switched to the reset state. The reset pulse is sequentially transferred to the inverting circuits I13 to I16 of the next stages, so that the states of the nodes 13 to 16 are sequentially switched to the reset state. Even after the 0th-round inversion 5, the transfer of the main pulse to the inverting circuit of the next stage continues, and the states of the nodes are sequentially switched to the set state.
Thereafter, in 0th-round inversion 10, the inverting circuit I1 is switched from the set state to the reset state according to the state of the node 16, so that the main pulse is reset and the state of the node 1 is switched to the reset state. The reset state of the main pulse is sequentially transferred to the inverting circuits of the next stages, so that the states of the nodes are sequentially switched to the reset state.
Thereafter, in the 0th-round inversion 16, the main pulse generated in the 0th-round inversion 1 circulates once within the ring oscillator circuit 180. In the next 1st-round inversion 1, the inverting circuit I1 is re-switched from the reset state to the set state, so that the next main pulse is generated. The next main pulse is sequentially transferred to the inverting circuits within the ring oscillator circuit 180, so that the nodes are sequentially switched to the set state.
After 1st-round inversion 4, the state of each node re-transitions to a state of 0th-round inversion 5.
Thereafter, 0th-round inversion 6 to 1st-round inversion 4 and 0th-round inversion 5 are iterated, so that the main pulse circulates around the inverting circuits I1 to I6 connected in the ring within the ring oscillator circuit 180.
As described above, the main pulse passes through the inverting circuits within the ring oscillator circuit 180. That is, the node state is switched from the reset state to the set state. In addition, the node state is switched from the set state to the reset state in advance by causing the reset pulse to pass through the inverting circuits before the main pulse. In this manner, the ring oscillator circuit 180 performs a stable oscillation operation by causing the main pulse and the reset pulse to circulate.
The time is converted into a digital value by detecting the number of inverting circuits (stages) through which an edge of the main pulse has passed and converting the detected number into a binary number.
In addition, resolution is one factor that determines the accuracy of the digital value. As described above, when the ring oscillator circuit 180 has been used for the purpose of converting the time into the digital value, a speed at which the main pulse passes through the inverting circuits within the ring oscillator circuit 180 determines the resolution of the digital value.
For example, when a predetermined constant time is converted into a digital value, it is possible to perform the conversion into a more highly accurate digital value in a ring oscillator circuit of inverting circuits of 40,000 stages through which the main pulse passes within the constant time than in a ring oscillator circuit of inverting circuits of only 40 stages through which the main pulse passes within the constant time at a low speed of the main pulse.
Here, the speed of the main pulse that passes through the inverting circuits within the ring oscillator circuit 180 will be described. FIGS. 14 and 15 are diagrams illustrating a relationship among operations of the inverting circuits and speeds of the main pulse and the reset pulse within the ring oscillator circuit 180 of the related art.
FIG. 14 illustrates an example of the states of the nodes within the ring oscillator circuit 180 when a speed of the main pulse that passes through the inverting circuits is lower than a speed of the reset pulse that passes through the inverting circuits. In addition, FIG. 15 illustrates an example of the states of the nodes within the ring oscillator circuit 180 when the speed of the main pulse that passes through the inverting circuits is higher than the speed of the reset pulse that passes through the inverting circuits. The viewpoints of view of FIGS. 14 and 15 are the same as that of FIG. 13.
The speeds of the main pulse and the reset pulse that pass through the inverting circuits within the ring oscillator circuit 180 can be adjusted, for example, by changing threshold voltages of the inverting circuits for each inverting circuit. More specifically, it is possible to set the speed of the reset pulse, which passes through the inverting circuits, to be higher than that of the main pulse by setting threshold voltages of the inverting circuits of the odd-numbered stages (the inverting circuits I1, I3, I5, I7, I9, I11, I13, and I15) within the ring oscillator circuit 180 to be high and setting threshold voltages of the inverting circuits of the even-numbered stages (the inverting circuits I2, I4, I6, I8, I10, I12, I14, and I16) to be low. That is, the speed of the main pulse can be set to be lower than that of the reset pulse. In addition, it is possible to set the speed of the reset pulse, which passes through the inverting circuits, to be lower than that of the main pulse by setting the threshold voltages of the inverting circuits of the odd-numbered stages within the ring oscillator circuit 180 to be low and setting the threshold voltages of the inverting circuits of the even-numbered stages to be high. That is, the speed of the main pulse can be set to be higher than the speed of the reset pulse.
The transition of the operation of the ring oscillator circuit 180 when the speed of the main pulse is lower than the speed of the reset pulse will be described with reference to FIG. 14. Even when the threshold voltages of the inverting circuits of the odd-numbered stages within the ring oscillator circuit 180 have been set to be high and the threshold voltages of the inverting circuits of the even-numbered stages set to be low, the main pulse and the reset pulse pass through the inverting circuits within the ring oscillator circuits 180 as in the transition of the basic operation of the ring oscillator circuit 180 illustrated in FIG. 13. At this time, when the speed of the reset pulse is higher than the speed of the main pulse, the reset pulse is quickly transferred to the inverting circuit I11 and the node 11 is switched to the reset state early in 1st-round inversion 3, for example, as illustrated in FIG. 14.
However, the inverting circuit I12 of the next stage is switched from the set state to the reset state according to the state of the node 4 by the main pulse being transferred to the inverting circuit I4 in subsequent inversion 4 of the first round. That is, after the inverting circuit I12 waits for the state of the node 4 to be switched to the set state by the main pulse in the inversion 4 of the first round, the inverting circuit I12 generates the next reset pulse by returning to 0th-round inversion 5 as the next inversion 5 of the first round.
As described above, because the inverting circuit I12 waits for the state of the node 4 to be switched in a state in which the speed of the main pulse is lower than the speed of the reset pulse, it is possible to iterate 0th-round inversion 6 to 1st-round inversion 4 and 0th-round inversion 5 as in the transition of the basic operation of the ring oscillator circuit 180 illustrated in FIG. 13. Thus, the circulation of the main pulse in the ring oscillator circuit 180 is not stopped, and a stable oscillation operation can be maintained.
The transition of the operation of the ring oscillator circuit 180 when the speed of the main pulse is higher than the speed of the reset pulse will be described with reference to FIG. 15. If the speed of the main pulse is high, it is possible to increase the number of stages of the inverting circuits through which the main pulse passes within a constant time. Thus, it is effective to improve the resolution of the digital value. Even when the threshold voltages of the inverting circuits of the odd-numbered stages within the ring oscillator circuit 180 have been set to be low and the threshold voltages of the inverting circuits of the even-numbered stages have been set to be high, the main pulse and the reset pulse pass through the inverting circuits within the ring oscillator circuit 180 as in the transition of the basic operation of the ring oscillator circuit 180 illustrated in FIG. 13. At this time, when the speed of the main pulse is higher than the speed of the reset pulse, that is, when the speed of the reset pulse is lower than the speed of the main pulse, for example, the node 11 is not switched to the reset state even in 1st-round inversion 4, and an interval between the reset pulse and the main pulse becomes narrow as illustrated in FIG. 15 as compared to the transition of the basic operation illustrated in FIG. 13.
Further, as a high-speed main pulse and a low-speed reset pulse undergo more circulations within the ring oscillator circuit 180, the interval between the reset pulse and the main pulse becomes narrower. Ultimately, the main pulse catches up with the reset pulse. In order to facilitate the understanding of this phenomenon, an example in which the interval between the reset pulse and the main pulse is narrowed by one stage every time the circulation is iterated as second and third circulations and the main pulse catches up with the reset pulse in 7th-round inversion 4 is illustrated in FIG. 15.
As described above, the main pulse catches up with the reset pulse in a state in which the speed of the main pulse is higher than the speed of the reset pulse. Accordingly, it may be impossible to maintain the same operation as in the transition of the basic operation of the ring oscillator circuit 180 illustrated in FIG. 13. In this case, the circulation of the main pulse in the ring oscillator circuit 180 is stopped, and it may be impossible to maintain a stable oscillation operation.
To avoid the circulation of the main pulse from being stopped due to this situation, an operation of setting the speed of the reset pulse to be higher than the speed of the main pulse is proposed in technology disclosed in Japanese Unexamined Patent Application, First Publication No. H06-216721.